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PCM-based Storage – A Game Changer?

by: admin Monday, June 6th, 2011

It looks like the ubiquitous NAND Flash memory is about to get some serious competition in the near future from Phase Change Memory (PCM), according to researchers from the University of California, San Diego (UCSD). They have built PCIe SSD prototypes called Moneta and Onyx based on PCM modules that delivers truly astonishing performance compared to the fastest NAND-based SSDs available today.

Moreover, they promise greatly improved durability, even compared to enterprise-class SLC NAND. Phase-Change Memory, like NAND, only lasts for so many write cycles, but PCM drives are vastly more robust than anything currently on the market. They will allegedly last for about 100,000,000 write cycles compared to 100,000 in today’s best enterprise SLC NAND (or approximately 3,000 write cycles in a current consumer-level 25nm MLC drive). If that’s not enough, PCM drives need less CPU and RAM (i.e. software) overhead to do the same thing as NAND SSDs, only much faster.

The Moneta array (emulated PCM) reaches a sustained bandwidth of 2.8GB/s and 541,000 random 4K IOPS, and 1.1M 512-byte IOPS. The teams Onyx prototype uses 1st generation Phase-Change Memory and produces 1.1GB/s for reads, but plans are underway to make it both faster and denser.

PCM is non-volatile just like NAND Flash, but work in an entirely different way. The technology uses the metal alloy chalcogenide to store data, and as the name implies the drives use a current to switch the alloy between the two states amorphous or crystalline. Although these drives are still at the development stage, the results so far look very promising and in a few years time this technology will no doubt be much faster as well as considerably more durable than conventional NAND.

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14 Responses to “PCM-based Storage – A Game Changer?”

vt Said:

There are some problems with PCM memory – closely placed cells require heat isolation otherwise writing into one cell may damage the data in the adjacent cells. It imposes restriction on the minimal size of a single PCM cell.
Also, the error rate grows with the temperature of the chip. Typical mass-produced PCM chips have 128 MBit capacity.
But i suppose they could stack more layers of silicon in one chip in the future.

Comment made on June 7th, 2011 at 12:23 am
admin Said:

That’s very interesting. They are careful to point out that this a 1st-gen prototype though, so a lot of things will probably happen before/if it’s universally adopted.

Comment made on June 7th, 2011 at 4:56 am
vt Said:

They just packed a lot of chips on the PCB. The chips are not that large, you can get a SSD with capacity comparable to HDD within a single standard 5.25-sized box by packing a lot of chips into it. Just it is is going to be expensive.
You can even get a MRAM SSD with a few gigabytes of raw capacity if you don’t care about the size. Each of such chips is 2 Mbytes (16 MBit) in size. 1000 chips = 2 gigabytes. Also, it is technologically possible to produce them up to 32 MBytes (256Mbit) per chip by stacking silicone into one chip, it would be just more expensive.

Comment made on June 7th, 2011 at 6:34 am
vt Said:

Also there is one very stupid PR myth about drives form factor. Actually there should be nothing wrong with 3.5 and 5.25 – sized SSDs (in desktop systems), but the makers of some products launched PR campaigns making people believe that they are “too large”. It is exceptionally stupid, and the people who believe it are even more stupid.
Actually 3.5 and 5.25 form factors are enough to pack up a required number of NAND SLC chips to be comparable to average HDDs in data capacity. With their mass-production capacities ranging up to 64Gbit per chip packing a required quantity of them is not a problem (there are only interconnect, cooling and interconnect problems with can be relatively easily solved).
The SLC NAND chips are already small enough to be of practical use. Any talks about their being to large are just stupid. There is hardly any need to actually reduce their dimensions or complain about their size in favor of MLC NAND chips (or even more pointless TLC NAND). What is happening now is a large-scale customer deception with PR means.
As a positive feedback about PCM memory – it is possible to stack multiple pieces of silicon to increase its capacity per chip as well. The adjacent cell overheating problem doesn’t spread across multiple silicon layers.

Comment made on June 8th, 2011 at 2:26 pm
vt Said:

correction – controllers, cooling and interconnect

Comment made on June 8th, 2011 at 2:28 pm
vt Said:

Interesting calculations: 1*1 meter area of MRAM high density chips would give 10000*2 = 20 gigabytes of raw capacity, the minimal height with PCB and controllers would be about 3 mm, it is possible to stack about 10 x layers of such PCBs vertically, which means that the same capacity can be placed on the area of 0.1 square meter, which means a box of 0.32*0.32 meters in size and 40 mm in height.
A standard 5.25 form factor would be enough to fit a few gigabytes of it (the limit is somewhere near 8 gigabytes), the only problem is the money and time required to build it.

Comment made on June 24th, 2011 at 2:27 pm
admin Said:

An interesting and somewhat discouraging calculation. It’s too bad that the “universal solution” MRAM is so far off.

Comment made on June 27th, 2011 at 4:19 pm
vt Said:

It is possible that there is a delay in high-capacity MRAM chips production because the major manufacturers want to get maximum profit from NAND. And it is likely they are going to continue suppressing any other technology – just to maximize their profits from the investments. Even with the current problems it is possible to produce MRAM chips with up to 2 gbits of raw capacity (there was some information about 1gbit chip a few years ago, with the current cell size it is possible to increase the capacity up to 2 gbits per chip).

Comment made on June 27th, 2011 at 11:58 pm
vt Said:

As a side note, it should be possible to fit about 16 TBytes of SLC chips into a single 5.25 case (with additional cooling and somewhat lower speed). With their density there are no problems with the physical dimensions. At present there are no problems with the dimensions for desktop and most server applications, regardless of what the PR assholes want to make the public believe in.

Comment made on July 2nd, 2011 at 2:19 am
vt Said:

Micron announced 300000 erase cycles NAND SLC chips (34 nm), but i’m not sure about their availability. If they are available, then the “best” SLC would be 300000 erase cycles, if not then 100000.

Comment made on July 9th, 2011 at 6:06 am
admin Said:

If i remember correctly, they are calling the 3000000 cycle SLC “Enterprise” SLC, but I have no idea either whether it’s actually used in any product today.

Comment made on July 10th, 2011 at 10:44 am
vt Said:

There are only products with “Enterprise MLC”, which has up to 30000 erase cycles. I have no idea either about their “Enterprise SLC”, i only saw the documents about its announcement, but nothing about its price or actual availability.

Comment made on July 10th, 2011 at 10:49 am
c Said:

I would like to know how many write cycles a computer uses before it hots craigslist?

I mean how many drives are being warn out from use rather than going out of date, I still love them SSD’s though.

Comment made on December 25th, 2011 at 6:46 am
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